TAIPEI, Taiwan, Feb. 2, Jan. 1, 2023 (GLOBE NEWSWIRE) — Alchip Technologies has become a founding member of TSMC’s 3DFabric™ Alliance by enhancing its 3nm process technology and advanced packaging capabilities.
The company supports the foundry program announced at the end of October, seeing it as a market driver to bring Alchip’s most advanced HPC ASIC technology to leading customer applications.
TSMC’s 3DFabric is a comprehensive family of 3D silicon stacking and advanced packaging technologies that unleash customer innovation in a system-level approach. It includes TSMC’s front-end technology or TSMC-SoIC™ (System on Integrated Chip), a dedicated fab for 3D stacked chip assembly and testing, and TSMC’s 3DFabric back-end technology, including CoWoS and InFO series packaging technologies.
The TSMC 3DFabric Alliance is the newest member of TSMC’s Open Innovation Platform® (OIP). New alliance partners will have early access to TSMC’s 3DFabric technology, enabling them to develop and optimize their solutions in parallel with TSMC. This gives customers early access to EDA, IP, memory, outsourced semiconductor assembly and test (OSAT), substrates and test.
“As a leader in high-performance computing ASICs, it is imperative for Alchip to join TSMC’s 3DFabric Alliance,” said Johnny Shen, President and CEO of Alchip. “This new initiative strengthens TSMC’s leadership in semiconductors by providing a leading high-performance ASIC company with a strategic opportunity to extend its state-of-the-art packaging capabilities to innovative technology customers.”
Alchip has been working with 3nm customer ASIC designs and taped out its first test chip in January 2023. It becomes the first dedicated high-performance ASIC company to declare overall design and production ecosystem readiness for TSMC’s latest N3E process technology.
In advanced packaging, Alchip is fine-tuning its industry-leading Chip-on-Substrate Safer (CoWoS®) packaging capabilities. CoWoS increases overall chip interconnect density and performance and is critical to almost all high-performance computing (HPC) ASICs.
CoWoS is a 2.5D wafer-level multi-chip packaging technology that integrates side-by-side die on a silicon interposer. Microbumps bond individual chips to the silicon interposer, forming chips on a wafer. Encapsulation is accomplished by bonding to the package substrate.
The CoWoS chipset consists of a high-performance system-on-chip (SoC) and a high-performance memory (HBM3 or HBM2E) block. Alchip’s CoWoS service covers all CoWoS package types such as CoWoS-S, CoWoS-R and CoWoS-L.
For more information on Alchip, visit www.alchip.com
About Alchip
Founded in 2003 and headquartered in Taipei, Taiwan, Alchip Technologies Ltd. is a leading global provider of silicon and design and production services for system companies developing complex and high-volume ASICs and SoCs. The company provides faster time-to-market and cost-effective solutions for mainstream and advanced SoC designs, including 7nm, 6nm, 5nm and 4nm processes. Alchip has built its reputation as a leader in high performance ASICs with its advanced 2.5D/3D packaging services, CoWoS/chiplet design and manufacturing experience. Customers include global leaders in artificial intelligence, high performance computing/supercomputers, mobile phones, entertainment devices, networking equipment and other electronics categories. Listed on the Taiwan Stock Exchange (TWSE: 3661), Alchip is a TSMC-certified value chain aggregator and a founding member of the new TSMC 3DFabric Alliance®.
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CoWoS chipset example
Charles Byers Alchip Technologies + (408)-310-9244 chuck_byers@alchip.com